M7020R datasheet(30/150 Pages) STMICROELECTRONICS

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M7020R

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READ COMMAND

The READ can be a single read of a data array, a

mask array, an SRAM, or a register location

(CMD[2] = 0). It can be a burst READ (CMD[2] = 1)

or mask array locations using an internal auto-in-

crementing address register (RBURADR). Table

18, page 32 describes each type of READ com-

mand.

A single-location READ operation lasts six cycles,

as shown in Figure 15, page 31. The burst READ

adds two cycles for each successive READ. The

SADR[21:20] bits supplied in the READ Instruction

Cycle A drive SADR[21:20] signals during the

READ of an SRAM location.

The single READ operation takes six CLK cycles,

in the following sequence:

– Cycle 1: The host ASIC applies the READ In-

struction on the CMD[1:0] (CMD[2] = 0), using

CMDV = 1, and the DQ Bus supplies the ad-

dress, as shown in Table 19, page 32 and Table

20, page 33. The host ASIC selects the M7020R

for which ID[4:0] matches the DQ[25:21] lines. If

the DQ[25:21] = 11111, the host ASIC selects

the M7020R with the LDEV Bit set. The host

ASIC also supplies SADR[21:20] on CMD[8:7]

in Cycle A of the READ Instruction if the READ

is directed to the external SRAM.

– Cycle 2: The host ASIC floats DQ[67:0] to 3-

state condition.

– Cycle 3: The host ASIC keeps DQ[67:0] in 3-

state condition.

– Cycle 4: The selected device starts to drive the

DQ[67:0] Bus and drives the ACK signal from Z

to low.

– Cycle 5: The selected device drives the read

data from the addressed location on the

DQ[67:0] Bus and drives the ACK signal high.

– Cycle 6: The selected device floats DQ[67:0] to

3-state condition and drives the ACK signal low.

At the termination of Cycle 6, the selected device

releases the ACK line to 3-state condition. The

READ Instruction is complete, and a new opera-

tion can begin.

Note: The latency of the SRAM READ will be dif-

ferent than the one described above (see SRAM

PIO Access, page 126). Table 19, page 32 lists

and describes the format of the READ address for

a data array, mask array, or SRAM.

In a burst READ operation, the READ lasts 4 + 2n

CLK-cycles (where “n” stands for the number of

accesses in the burst specified by the BLEN field

of the RBURREG). Table 20, page 33 describes

the READ address format for the internal registers.

Figure 16, page 31 illustrates the timing diagram

for the burst READ of the data or mask array. This

operation assumes that the host ASIC has pro-

grammed the RBURREG with the starting address

(ADR) and the length of transfer (BLEN) before ini-

tiating the burst READ command.

– Cycle 1: The host ASIC applies the READ In-

struction on the CMD[1:0] (CMD[2] = 1), using

CMDV=1 and the address supplied on the DQ

Bus, as shown in Table 21, page 33. The host

ASIC selects the M7020R for which ID[4:0]

matches the DQ[25:21] lines. If the DQ[25:21] =

11111, the host ASIC selects the M7020R with

the LDEV Bit set.

– Cycle 2: The host ASIC floats DQ[67:0] to the 3-

state condition.

– Cycle 3: The host ASIC keeps DQ[67:0] in the

3-state condition.

– Cycle 4: The selected device starts to drive the

DQ[67:0] Bus and drives ACK and EOT from Z

to low.

– Cycle 5: The selected device drives the READ

data from the addressed location on the

DQ[67:0] Bus and drives the ACK signal high.

Note: Cycles four and five repeat for each addi-

tional access until all the accesses specified in

the burst length (BLEN) field of RBURREG are

complete. On the last transfer, the M7020R

drives the EOT signal high.

– Cycle (4 + 2n): The selected device drives the

DQ[67:0] to 3-state condition and drives the

ACK and the EOT signals low.

At the termination of Cycle 4 + 2n, the selected de-

vice floats the ACK line to 3-state condition. The

burst READ Instruction is complete, and a new op-

eration can begin (see Table 21, page 33 for burst

READ address formats).

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