M7020R datasheet(35/150 Pages) STMICROELECTRONICS

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M7020R

Figure 18. Burst WRITE of the Data and Mask Arrays (BLEN = 4)

Table 22. (Single) WRITE Address Format for Data and Mask Arrays or SRAM

Note: 1. “|” stands for Logical OR operation. “{ }” stands for concatenation operator.

[67:30]

[29]

[28:26]

[25:21]

[20:19]

[18:15]

[14:0]

Reserved

0: Direct

1: Indirect

Successful

Index

(Applicable

if DQ[29] is

indirect)

00: Data

Array

Reserved

If DQ[29] is ’0,’ this field carries the

address of the data array location.

If DQ[29] is ’1,’ the successful

search register specified by

DQ[28:26] supplies the address of

the data array location:

{SSR[14:2], SSR[1] | DQ[1], SSR[0]

| DQ[0]}(1)

Reserved

0: Direct

1: Indirect

Successful

Index

(Applicable

if DQ[29] is

indirect)

01: Mask

Array

Reserved

If DQ[29] is ’0,’ this field carries

address of the mask array location.

If DQ[29] is ’1,’ the successful

search register specified by

DQ[28:26] supplies the address of

the mask array location:

{SSR[14:2], SSR[1] | DQ[1], SSR[0]

| DQ[0]}(1)

Reserved

0: Direct

1: Indirect

Successful

Index

(Applicable

if DQ[29] is

indirect)

10:

External

SRAM

Reserved

If DQ[29] is ’0,’ this field carries

address of the data SRAM location.

If DQ[29] is ’1,’ the successful

search register specified by

DQ[28:26] supplies the address of

the SRAM location:

{SSR[14:2], SSR[1] | DQ[1], SSR[0]

| DQ[0]}(1)

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 6

CLK2X

CMDV

CMD[1:0]

EOT

PHS_L

AI04285

Write

CMD[8:2]

Address

Data0

Data1

Data2

Data3

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