M7020R datasheet(46/150 Pages) STMICROELECTRONICS

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M7020R

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Table 28. Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, Up to 8 Devices

Table 29. Shift of SSF and SSV from SADR

68-bit SEARCH on Tables Configured as x68 Using Up To 31 M7020R Devices

The hardware diagram of the search subsystem of

31 devices is shown in Figure 27, page 48. Each

of the four blocks in the diagram represents eight

M7020R devices (except the last, which has seven

devices). The diagram for a block of eight devices

is shown in Figure 28, page 49. The following are

the parameters programmed into the 31 devices:

– First thirty devices (devices 0–29):

CFG = 00000000, TLSZ = 10, HLAT = 001,

LRAM = 0, and LDEV = 0.

– Thirty-first device (device 30):

CFG = 00000000, TLSZ = 10, HLAT = 001,

LRAM = 1, and LDEV = 1.

Note: All 31 devices must be programmed with the

same values for TLSZ and HLAT. Only the last de-

vice in the table must be programmed with

LRAM = 1 and LDEV = 1 (Device 30 in this case).

All other upstream devices must be programmed

with LRAM = 0 and LDEV = 0 (Devices 0 through

29 in this case).

The timing diagrams referred to in this paragraph

reference the HIT/MISS assumptions defined in

Table 30, page 47. For the purpose of illustrating

the timings, it is further assumed that there is only

one device with a matching entry in each of the

blocks. Figure 30, page 51 shows the timing dia-

gram for a SEARCH command in the 68-bit-con-

figured table of 31 devices for each of the eight

devices in Block Number 0. Figure 31, page 52

shows a timing diagram for a SEARCH command

in the 68-bit-configured table of 31 devices for the

all the devices in Block Number 1 (above the win-

ning device in that block). Figure 32, page 53

shows the timing diagram for the globally winning

device (defined as the final winner within its own

and all blocks) in Block Number 1. Figure 33, page

54 shows the timing diagram for all the devices be-

low the globally winning device in Block Number 1.

Figure 34, page 55, Figure 35, page 56, and Fig-

ure 36, page 57 show the timing diagrams of the

devices above the globally winning device, the glo-

bally winning device, and the devices below the

globally winning device, respectively, for Block

Number 2. Figure 37, page 58, Figure 38, page 59,

Figure 39, page 60, and Figure 40, page 61 show

the timing diagrams of the devices above globally

winning device, the globally winning device, and

the devices below the globally winning device ex-

cept the last device (Device 30), respectively, for

Block Number 3.

# of devices

Max Table Size

Latency in CLK Cycles

1 (TLSZ = 00)

32K x 68-bit

2–8 (TLSZ = 01)

256K x 68-bit

9–31 (TLSZ = 10)

992K x 68-bit

HLAT

Number of CLK Cycles

000

001

010

011

100

101

110

111

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