R5F5651EDDFM datasheet(159/188 Pages) RENESAS

159 / 188 page

R01DS0276EJ0240 Rev.2.40

Page 159 of 188

Oct 31, 2023

RX65N Group, RX651 Group

2. Electrical Characteristics

2.4.7.18

SDSI

Note 1. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in

combination with the pins in the same group. All SDSI AC timings are measured in combination with the pins in the same group.

Figure 2.83

SD Slave Interface Input Signal Timing

Table 2.46

SDSI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit

Test Conditions*1

SDSI

SDSI_CLK pin input cycle time

tPP(SDSI)

—

Figure 2.83

SDSI_CLK pin input high pulse width

tWH(SDSI)

0.4 ×

tPP(SDSI)

—ns

SDSI_CLK pin input low pulse width

tWL(SDSI)

0.4 ×

tPP(SDSI)

—ns

SDSI_CLK pin input rise time

tTLH(SDSI)

—3

SDSI_CLK pin input fall time

tTHL(SDSI)

—3

Input data setup time for SDSI_CMD and SDSI_D0 to

SDSI_D3 pins

tISU(SDSI)

5—

Input data hold time for SDSI_CMD and SDSI_D0 to

SDSI_D3 pins

tIH(SDSI)

2—

Output data delay time for SDSI_CMD and SDSI_D0

to SDSI_D3 pins (default speed mode)

tODLY(SDSI)

Figure 2.84

Output data delay time for SDSI_CMD and SDSI_D0

to SDSI_D3 pins (high speed mode)

2.5

Figure 2.85

SDSI_CLK input

SDSI_CMD, SDSI_D3 to SDSI_D0 input

tWL(SDSI)

tWH(SDSI)

tPP(SDSI)

tISU(SDSI) tIH(SDSI)

tTLH(SDSI)

tTHL(SDSI)

VIH

VIL

VIH

50% VCC

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