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RZ/A1M Datasheet(PDF) 76 Page - Renesas Technology Corp

Part # RZ/A1M
Description  RZ/A1H Group, RZ/A1M Group
PDF  137 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RZ/A1M Datasheet(HTML) 76 Page - Renesas Technology Corp

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R01DS0479EJ0100 Rev.1.00
Page 76 of 137
Dec. 25, 2024
RZ/A1H Group, RZ/A1M Group
3. Electrical Characteristics
Figure 3.19
Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, CAS Latency 2,
WTRCD = 0 Cycle, WTRP = 1 Cycle)
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Tc1
Tc2
Td1
Td2
Td3
Td4
Tr
Tc3
Tc4
Tde
t
AD1
t
AD1
t
CSD1
t
AD1
t
AD1
t
AD1
t
AD1
t
RWD1
t
RWD1
t
CSD1
t
AD1
t
AD1
t
AD1
t
AD1
t
RDH2
t
RDS2
CKIO
A25 to A0
CSn
RD/
WR
A12/A11
*1
D31 to D0
t
RASD1
t
RASD1
RAS
Row
address
READA
command
READ command
Column
address
(1 to 4)
tCASD1
t
CASD1
CAS
t
BSD
t
BSD
(High)
BS
CKE
t
DQMD1
tDQMD1
DQMxx
tDACD
t
DACD
DACKn
TENDn*2
t
RDH2
t
RDS2



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