RZSLASHA1M datasheet(95/137 Pages) RENESAS

95 / 137 page

R01DS0479EJ0100 Rev.1.00

Page 95 of 137

Dec. 25, 2024

RZ/A1H Group, RZ/A1M Group

3. Electrical Characteristics

3.4.8

Serial Communication Interface Timing

Note:

tp1cyc indicates the peripheral clock 1 (P1

) cycle.

Figure 3.40

SCK Input Clock Timing

Figure 3.41

Transmit/Receive Data Input/Output Timing in Clocked Synchronous Mode

Table 3.12

Serial Communication Interface Timing

Item

Symbol

Min.

Max.

Unit

Figure

Input clock cycle

(asynchronous)

tScyc

4―

tp1cyc

Figure 3.40

(clocked synchronous)

―

Input clock pulse width

tSCKW

0.4

0.6

tScyc

Input clock rise time

tSCKr

―20

Input clock fall time

tSCKf

―20

Output clock cycle

(asynchronous)

tScyc

―

tp1cyc

(clocked synchronous)

―

Output clock pulse width

tSCKW

0.4

0.6

tScyc

Output clock rise time

tSCKr

―20

Output clock fall time

tSCKf

―20

Transmit data delay time (clocked synchronous)

tTXD

―

Figure 3.41

Receive data setup time

(clocked synchronous)

tRXS

―

Receive data hold time

(clocked synchronous)

tRXH

―

SCKW

SCKr

SCKf

Scyc

SCKn

(n = 0, 1)

TXD

SCKW

SCKn

TXDn

RXDn

(n = 0, 1)

RXH

RXS

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