NRF52810-QFAA-R datasheet(427/483 Pages) NORDIC

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Peripherals

Symbol

Type

Description

ENABLE

The TWI slave has been enabled via the ENABLE register

PREPARETX

Task

The TASKS_PREPARETX task has been triggered

STOP

Task

The TASKS_STOP task has been triggered

PREPARERX

Task

The TASKS_PREPARERX task has been triggered

STOPPED

Event

The EVENTS_STOPPED event was generated

RXSTARTED

Event

The EVENTS_RXSTARTED event was generated

TXSTARTED

Event

The EVENTS_TXSTARTED event was generated

TX prepared

Internal

Internal flag indicating that a TASKS_PREPARETX task has been triggered. This flag is not visible to the

user.

RX prepared

Internal

Internal flag indicating that a TASKS_PREPARERX task has been triggered. This flag is not visible to the

user.

Unprepare TX

Internal

Clears the internal 'TX prepared' flag until next TASKS_PREPARETX task.

Unprepare RX

Internal

Clears the internal 'RX prepared' flag until next TASKS_PREPARERX task.

Stop sequence

TWI protocol

A TWI stop sequence was detected

Restart sequence

TWI protocol

A TWI restart sequence was detected

Table 89: TWI slave state machine symbols

The TWI slave supports clock stretching performed by the master.

The TWI slave operates in a low power mode while waiting for a TWI master to initiate a transfer. As long

as the TWI slave is not addressed, it will remain in this low power mode.

To secure correct behaviour of the TWI slave, PSEL.SCL, PSEL.SDA, CONFIG and the ADDRESS[n] registers,

must be configured prior to enabling the TWI slave through the ENABLE register. Similarly, changing these

settings must be performed while the TWI slave is disabled. Failing to do so may result in unpredictable

behaviour.

6.24.1 EasyDMA

The TWI slave implements EasyDMA for reading and writing to and from the RAM.

The STOPPED event indicates that EasyDMA has finished accessing the buffer in RAM.

If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result

in a HardFault or RAM corruption. See Memory on page 15 for more information about the different

memory regions.

6.24.2 TWI slave responding to a read command

Before the TWI slave can respond to a read command the TWI slave must be configured correctly and

enabled via the ENABLE register. When enabled the TWI slave will be in its IDLE state where it will

consume IIDLE .

A read command is started when the TWI master generates a start condition on the TWI bus, followed

by clocking out the address and the READ/WRITE bit set to 1 (WRITE=0, READ=1). The READ/WRITE bit is

followed by an ACK/NACK bit (ACK=0 or NACK=1) response from the TWI slave.

The TWI slave is able to listen for up to two addresses at the same time. Which addresses to listen for is

configured in the ADDRESS registers and the CONFIG register.

The TWI slave will only acknowledge (ACK) the read command if the address presented by the master

matches one of the addresses the slave is configured to listen for. The TWI slave will generate a READ

event when it acknowledges the read command.

The TWI slave is only able to detect a read command from the IDLE state.

The TWI slave will set an internal 'TX prepared' flag when the PREPARETX task is triggered.

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