NRF52810-QFAA-R datasheet(256/483 Pages) NORDIC

256 / 483 page

Peripherals

6.12.2 Decoder with EasyDMA

The decoder uses EasyDMA to take PWM parameters stored in Data RAM by ways of EasyDMA and

updates the internal compare registers of the wave counter based on the mode of operation.

The mentioned PWM parameters are organized into a sequence containing at least one half word (16 bit).

Its most significant bit[15] denotes the polarity of the OUT[n] while bit[14:0] is the 15-bit compare value.

See below for further details of these RAM defined registers.

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

B A A A A A A A A A A A A A A A

Reset 0x00000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RW Field

Value Id

Value

Description

RW COMPARE

Duty cycle setting - value loaded to internal compare

RW POLARITY

Edge polarity of GPIO.

RisingEdge

First edge within the PWM period is rising

FallingEdge

First edge within the PWM period is falling

The DECODER register controls how the RAM content is interpreted and loaded to the internal compare

registers. The LOAD field can be used to control if the RAM values are loaded to all compare channels -

or alternatively to update a group or all channels with individual values. Decoder memory access modes

on page 257 illustrates how the parameters stored in RAM are organized and routed to the various

compare channels in the different modes.

A special mode of operation is available when DECODER.LOAD is set to WaveForm. In this mode, up to

three PWM channels can be enabled - OUT[0] to OUT[2]. In RAM, four values are loaded at a time: the

first, second and third location are used to load the values, and the fourth RAM location is used to load

the COUNTERTOP register. This way one can have up to three PWM channels with a frequency base that

changes on a per PWM period basis. This mode of operation is useful for arbitrary wave form generation

in applications such as LED lighting.

The register SEQ[n].REFRESH=N (one per sequence n=0 or 1) will instruct a new RAM stored pulse width

value on every (N+1)th PWM period. Setting the register to zero will result in a new duty cycle update

every PWM period as long as the minimum PWM period is observed.

Note that registers SEQ[n].REFRESH and SEQ[n].ENDDELAY are ignored when DECODER.MODE=NextStep .

The next value is loaded upon receiving every NEXTSTEP task.

4430_161 v1.0

256

NRF52810-QFAA-R Datasheet(PDF) 256 Page - Nordic Semiconductor

NRF52810-QFAA-R Datasheet(HTML) 256 Page - Nordic Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL