NRF52820-QDAA-R7 datasheet(57/437 Pages) NORDIC

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Power and clock management

Configuration

RAM section status

System on/off

RAM[n].POWER.POWER

RAM[n].POWER.RETENTION Accessible

Retained

Off

Yes

Off

Off3

Yes

Table 15: RAM section configuration

The advantage of not retaining RAM contents is that the overall current consumption is reduced.

See Memory on page 15 for more information on RAM sections.

5.3.6 Reset

Several sources may trigger a reset.

After a reset has occurred, register RESETREAS can be read to determine which source triggered the reset.

5.3.6.1 Power-on reset

The power-on reset generator initializes the system at power-on.

The system is held in reset state until the supply has reached the minimum operating voltage and the

internal voltage regulators have started.

5.3.6.2 Pin reset

A pin reset is generated when the physical reset pin on the device is asserted.

Pin reset is configured via both registers PSELRESET[n] (n=0..1) on page 35.

5.3.6.3 Wakeup from System OFF mode reset

The device is reset when it wakes up from System OFF mode.

The debug access port (DAP) is not reset following a wake up from System OFF mode if the device is in

Debug Interface mode. See chapter Debug on page 40 for more information.

5.3.6.4 Soft reset

A soft reset is generated when the SYSRESETREQ bit of the application interrupt and reset control register

(AIRCR) in the ARM® core is set.

See ARM documentation for more details.

A soft reset can also be generated via the register RESET on page 41 in the CTRL-AP.

5.3.6.5 Watchdog reset

A Watchdog reset is generated when the watchdog times out.

See chapter WDT — Watchdog timer on page 410 for more information.

5.3.6.6 Brownout reset

The brownout reset generator puts the system in a reset state if VDD drops below the brownout reset

(BOR) threshold.

See section Power fail comparator on page 68 for more information.

3 Not useful. RAM section power off gives negligible reduction in current consumption when retention

is on.

4463_156 v1.0

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