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NRF52811-QCAA-R7 Datasheet(PDF) 410 Page - Nordic Semiconductor |
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NRF52811-QCAA-R7 Datasheet(HTML) 410 Page - Nordic Semiconductor |
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410 / 444 page  Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field Value ID Value Description A R AMOUNT [1..0x3FF] Number of bytes transferred in the last transaction 6.28.9.34 CONFIG Address offset: 0x56C Configuration of parity and hardware flow control Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B B B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field Value ID Value Description A RW HWFC Hardware flow control Disabled 0 Disabled Enabled 1 Enabled B RW PARITY Parity Excluded 0x0 Exclude parity bit Included 0x7 Include even parity bit C RW STOP Stop bits One 0 One stop bit Two 1 Two stop bits 6.28.10 Electrical specification 6.28.10.1 UARTE electrical specification Symbol Description Min. Typ. Max. Units fUARTE Baud rate for UARTE33. 1000 kbps tUARTE,CTSH CTS high time 1 µs tUARTE,START Time from STARTRX/STARTTX task to transmission started .. .. .. µs 6.29 WDT — Watchdog timer A countdown watchdog timer using the low-frequency clock source (LFCLK) offers configurable and robust protection against application lock-up. The watchdog timer is started by triggering the START task. The watchdog can be paused during long CPU sleep periods for low power applications and when the debugger has halted the CPU. The watchdog is implemented as a down-counter that generates a TIMEOUT event when it wraps over after counting down to 0. When the watchdog timer is started through the START task, the watchdog counter is loaded with the value specified in the CRV register. This counter is also reloaded with the value specified in the CRV register when a reload request is granted. 33 High baud rates may require GPIOs to be set as High Drive, see GPIO chapter for more details. 4454_140 v1.0 410 |
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