NRF52811-QCAA-R datasheet(347/444 Pages) NORDIC

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Peripherals

SDA

RXD-1

TXD+1

EasyDMA

RXD.PTR

TXD.PTR

buffer[0]

buffer[1]

buffer[RXD.MAXCNT-1]

RAM

buffer[0]

buffer[1]

buffer[TXD.MAXCNT-1]

PSEL.SDA

GPIO

PSEL.SCK

TWIM

TXD buffer

RXD buffer

SCL

Figure 129: TWI master with EasyDMA

A typical TWI setup consists of one master and one or more slaves. For an example, see A typical TWI

setup comprising one master and three slaves on page 347. This TWIM is only able to operate as a

single master on the TWI bus. Multi-master bus configuration is not supported.

TWI master

(TWIM)

TWI slave

(Sensor)

Address = b1011000

TWI slave

Address = b1011011

SCL

TWI slave

(EEPROM)

Address = b1011001

SCL

VDD

SDA

SCL

SDA

Figure 130: A typical TWI setup comprising one master and three slaves

This TWI master supports clock stretching performed by the slaves. Note that the SCK pulse following a

stretched clock cycle may be shorter than specified by the I2C specification.

The TWI master is started by triggering the STARTTX or STARTRX tasks, and stopped by triggering the STOP

task. The TWI master will generate a STOPPED event when it has stopped following a STOP task. The TWI

master cannot get stopped while it is suspended, so the STOP task has to be issued after the TWI master

has been resumed.

After the TWI master is started, the STARTTX task or the STARTRX task should not be triggered again

before the TWI master has stopped, i.e. following a LASTRX, LASTTX or STOPPED event.

If a NACK is clocked in from the slave, the TWI master will generate an ERROR event.

6.25.1 EasyDMA

The TWIM implements EasyDMA for accessing RAM without CPU involvement.

The TWIM peripheral implements the following EasyDMA channels:

4454_140 v1.0

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NRF52811-QCAA-R Datasheet(PDF) 347 Page - Nordic Semiconductor

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