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L6713ATR Datasheet(PDF) 28 Page - STMicroelectronics

Part # L6713ATR
Description  2/3 phase controller with embedded drivers for Intel VR10, VR11 and AMD 6 bit CPUs
PDF  64 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L6713ATR Datasheet(HTML) 28 Page - STMicroelectronics

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Configuring the device
L6713A
28/64
8
Configuring the device
Number of phases and multiple DACs need to be configured before the system starts-up by
programming the apposite pin PHASE_SEL and SS/LTBG/AMD pin.
The configuration of this pin identifies two main working areas (See Table 12) distinguishing
between compliancy with Intel VR10,VR11 or AMD 6BIT specifications. According to the
main specification considered, further customizations can be done: main differences are
regarding the DAC table, soft-start implementation, protection management and Dynamic
VID Transitions. See Table 13 and See Table 14 for further details about the device
configuration.
8.1
Number of phases selection
L6713A allows to select between two and three phase operation simply using the
PHASE_SEL pin, as shown in the following table.
8.2
DAC selection
L6713A embeds a selectable DAC (through SS/LTBG/AMD pin, See Table 12) that allows to
regulate the output voltage with a tolerance of ±0.5% (±0.6% for AMD DAC) recovering from
offsets and manufacturing variations. In case of selecting Intel mode, the device
automatically introduces a -19 mV (both VRD10.x and VR11) offset to the regulated voltage
in order to avoid any external offset circuitry to worsen the guaranteed accuracy and, as a
consequence, the calculated system TOB.
Note:
When selecting Intel mode, SS/LTBG/AMD pin is used to select both soft-start time and
LTBgain (see dedicated sections).
Table 11.
Number of phases setting
PHASE_SEL pin
Number of phases
Phases used
Floating
2-PHASE
Phase1, Phase3
Short to SGND
3-PHASE
Phase1, Phase2, Phase3
Table 12.
DAC settings (See note)
SS / LTBG / AMD
Resistor (RSSOSC)
vs. SGND
DAC
Soft-start time
LTBgain
OVP
UVP
0 (Short)
AMD
Not
programmable
Fixed
(LTBgain = 2)
1.800 V (typ)
or
Programmable
-750 mV
(typ)
> 2.4 k
Ω
Intel
Programmable
trough RSSOSC
Programmable
trough RSSOSC
(LTBgain
≤ 2)
VID + 175 mV
(typ)
or
programmable
-750 mV
(typ)



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