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STV0056 Datasheet(PDF) 15 Page - STMicroelectronics |
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STV0056 Datasheet(HTML) 15 Page - STMicroelectronics |
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15 / 26 page ![]() 180 µ/2µ MUX 100 µ/2µ I/O/22kHz 10 µ/2µ 91 µ/2µ 205 Ω ESD IIC Reg 22kHz Figure 15 SCL 24 µ/4µ 205 Ω ESD Figure 16 SDA 24 µ/4µ 205 Ω ESD 600 µ/2µ GND 0V Figure 17 J17 L J17 R U75 L U75 R I2 I1 Figure 18 HA 25 µ/2µ 10 µ/2µ 205 Ω ESD GND 0V 150 µA Figure 19 750 µA 460 Ω XTL GND 0V 2 3 2 500 µA 5pF 460 Ω 3 750 µA Figure 20 CPUMP L CPUMP R VCO Input 1 µA 1 µA Loop Filter Tracking 100 µA 100 µA Dig Synth Figure 21 DET L DET R I2 I1 Figure 22 PIN INTERNAL CIRCUITRY (continued) I/O / 22kHz The input is TTL compatible. The output is tri-stateable. SCL This is the input to a Schmitt input buffer made with a CMOS amplifier. SDA Input same as above. Output pull down only : relies on external resistor for pull-up. J17 L, J17 R, U75 L, U75 R I1 - I2 = 2 x audio / 18k Ω. eg 1VPP audio : ±55µA. The are internal switches to match the audio level of the different standards. HA Pull-down current for SDIP42. Input with CMOS levels. XTL CPUMP L, CPUMP R An offset on the PLL loop filter will cause an offset in the two 1 µA currents that will prevent the PLL from drifting-off frequency. DET L, DET R I2 - I1 = f (phase error). STV0056A 15/26 |
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