DS72011RB120FPV datasheet(331/1196 Pages) RENESAS

331 / 1196 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 303 of 1164

REJ09B0321-0200

Figure 11.1 is a block diagram of the DMAC

CPU

I/F

DMAC Core

DMAC

DMA end

DMA acknowledge

DMA active

DMA interrupt request

DMA common

interrupt request

CPU control

signal

DMA request transfer

Current

Reload

Ch0 DMA setting data

Chn DMA setting data

Ch0 DMA transfer data

Chn DMA transfer data

On-chip memory

DMA request from

outside (DREQ) or

on-chip peripheral circuit

Memory I/F

(Work register)

Memory load/store

control

Source address

Destination address

Byte count register

Mode register

DMAC

control

circuit

Data

buffer

DMAC

control signal

[Legend]

DMA request transfer: Arbitration of DMA requests and generation of request signal to DMAC core

CPU I/F:

Read/write control of register access from CPU

Memory I/F:

Memory access control from CPU and DMAC core

On-chip memory:

Stores DMAC setting data and transfer data

Work register:

DMAC control circuit: DMAC control circuit

Data buffer:

DMA data buffer

Figure 11.1 DMAC Block Diagram

11.2

Input/Output Pins

Table 11.1

Pin Configuration

Name

I/O

Function

DREQm (m

= 0 to 3)

Input

External request for DMA transfer

DACKm (m

= 0 to 3)

Output

DMA acknowledgement of external request for DMA transfer

(active low)

DACTm (m

= 0 to 3)

Output

DMA active in externally requested DMA transfer (active low)

DTENDm (m

= 0 to 3)

Output

Completion of externally requested DMA transfer (active low)

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