DS72011RB120FPV datasheet(296/1196 Pages) RENESAS

Part #	DS72011RB120FPV

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 268 of 1164

REJ09B0321-0200

(d)

Timing Register Set Values and Access Timing

The correspondence between the SDRAMm timing register (SDmTR) set values and the read and

write access timing is described below.

• Multiple Read Timing Setting Examples

Figures 9.30 to 9.32 show the correspondence between the timing of multiple read operations

involving 4 data units and the set values of the SDRAMm timing register (SDmTR). Table

9.12 shows the SDRAMm timing register (SDmTR) set values for each figure.

Table 9.12

SDITR Set Value Correspondence Table (Multiple Read Timing)

Figure

DRAS

DRCD

DPCG

DCL

Figure 9.30

010

001

010

Figure 9.31

000

001

010

Figure 9.32

000

001

011

CKIO

ACT: Row and bank activation command

RD:

Read command

PRA: Precharge-all command

SDRAM command

Data bus

Multiple read

ACT

PRA

DSL

DRCD

(ACT-RD)

DRAS

(ACT-PRA)

DCL

(RD-d)

DPCG

(PRA-next)

Figure 9.30 Multiple Read Timing Example 1

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