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DS72011RB120FPV Datasheet(PDF) 299 Page - Renesas Technology Corp

Part # DS72011RB120FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
PDF  1196 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

DS72011RB120FPV Datasheet(HTML) 299 Page - Renesas Technology Corp

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Section 9 Bus State Controller (BSC)
Rev. 2.00 Sep. 07, 2007 Page 271 of 1164
REJ09B0321-0200
CKIO
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all command
SDRAM command
Data bus
Multiple write
ACT
DSL
WR
WR
WR
WR
PRA
DSL
d0
DRCD
(ACR-WR)
DRAS
(ACT-PRA)
DWR
(WR-PRA)
DPCG
(PRA-next)
d1
d2
d3
Figure 9.34 Multiple Write Timing Example 2
CKIO
ACT: Row and bank activation command
WR:
Write command
PRA: Precharge-all command
SDRAM command
Data bus
Multiple write
ACT
DSL
WR
WR
WR
WR
DSL
PRA
DSL
d0
DRCD
(ACT-WR)
DRAS
(ACT-PRA)
DWR
(WR-PRA)
DPCG
(PRA-next)
d1
d2
d3
Figure 9.35 Multiple Write Timing Example 3
• Single Read Timing Setting Examples
Figures 9.36 to 9.38 show the correspondence between the timing of single read operations and
the set values of the SDRAMm timing register (SDmTR). Table 9.14 shows the SDRAMm
timing register (SDmTR) set values for each figure.



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