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DS72011RB120FPV Datasheet(PDF) 303 Page - Renesas Technology Corp |
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DS72011RB120FPV Datasheet(HTML) 303 Page - Renesas Technology Corp |
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303 / 1196 page  Section 9 Bus State Controller (BSC) Rev. 2.00 Sep. 07, 2007 Page 275 of 1164 REJ09B0321-0200 CKIO ACT: Row and bank activation command WR: Write command DSL: Deselect command PRA: Precharge-all command SDRAM command Data bus Single write Note: If the interval set in DRAS is longer than the period from when the WR command is issued until the DRAS interval elapses, the DWR setting is used. ACT DSL WR PRA DSL DRCD (ACT-WR) DWR (WR-PRA) DPCG (PRA-next) DRAS (ACT-PRA) d Figure 9.40 Single Write Timing Example 2 CKIO ACT: Row and bank activation command WR: Write command DSL: Deselect command PRA: Precharge-all command SDRAM command Data bus Single write ACT DSL WR DSL PRA DSL DRCD (ACT-WR) DWR (WR-PRA) DPCG (PRA-next) DRAS (ACT-PRA) d Figure 9.41 Single Write Timing Example 3 |
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