R5F72115D160FPV datasheet(647/1228 Pages) RENESAS

647 / 1228 page

Section 12 Port Output Enable 2 (POE2)

Rev. 2.00 May. 08, 2008 Page 623 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

POE8F

R/(W)*

POE8 Flag

Indicates that a high impedance request has been input

to the

POE8 pin.

[Clearing conditions]

• By writing 0 to POE8F after reading POE8F = 1

(when the falling edge is selected by bits 1 and 0 in

ICSR3)

• By writing 0 to POE8F after reading POE8F = 1 after

a high level input to

POE8 is sampled at Pφ/8, Pφ/16,

or P

φ/128 clock (when low-level sampling is selected

by bits 1 and 0 in ICSR3)

[Setting condition]

• When the input condition set by bits 1 and 0 in

ICSR3 occurs at the

POE8 pin

11, 10

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

POE8E

R/W*

POE8 High-Impedance Enable

Specifies whether to place the pins in high-impedance

state when the POE8F bit in ICSR3 is set

to 1.

0: Does not place the pins in high-impedance state

1: Places the pins in high-impedance state

PIE3

R/W

Port Interrupt Enable 3

Enables or disables interrupt requests when the POE8

bit in ICSR3 is set to 1.

0: Interrupt requests disabled

1: Interrupt requests enabled

7 to 2

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

R5F72115D160FPV Datasheet(PDF) 647 Page - Renesas Technology Corp

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