R5F72115D160FPV datasheet(650/1228 Pages) RENESAS

650 / 1228 page

Section 12 Port Output Enable 2 (POE2)

Rev. 2.00 May. 08, 2008 Page 626 of 1200

REJ09B0344-0200

12.3.7

Port Output Enable Control Register 1 (POECR1)

POECR1 is an 8-bit readable/writable register that controls high-impedance state of the pins.

7654321

00000000

RRRR

R/W* R/W* R/W* R/W*

Bit:

Initial value:

R/W:

Note:

Can be modified only once after a power-on reset.

----

MTU2

PA24ZE

MTU2

PA25ZE

MTU2

PA23ZE

MTU2

PA22ZE

Bit

Bit Name

Initial

Value

R/W

Description

7 to 4

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

MTU2PA25ZE 0

R/W*

MTU2PA25 High-Impedance Enable

Specifies whether to place the PA25/TIOC0D pin for

channel 0 in the MTU2 in high-impedance state when

either POE8F or MTU2CH0HIZ bit is set to 1.

0: Does not place the pin in high-impedance state

1: Places the pin in high-impedance state

MTU2PA24ZE 0

R/W*

MTU2PA24 High-Impedance Enable

Specifies whether to place the PA24/TIOC0C pin for

channel 0 in the MTU2 in high-impedance state when

either POE8F or MTU2CH0HIZ bit is set to 1.

0: Does not place the pin in high-impedance state

1: Places the pin in high-impedance state

MTU2PA23ZE 0

R/W*

MTU2PA23 High-Impedance Enable

Specifies whether to place the PA23/TIOC0B pin for

channel 0 in the MTU2 in high-impedance state when

either POE8F or MTU2CH0HIZ bit is set to 1.

0: Does not place the pin in high-impedance state

1: Places the pin in high-impedance state

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