R5F72115D160FPV datasheet(651/1228 Pages) RENESAS

651 / 1228 page

Section 12 Port Output Enable 2 (POE2)

Rev. 2.00 May. 08, 2008 Page 627 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

MTU2PA22ZE 0

R/W*

MTU2PA22 High-Impedance Enable

Specifies whether to place the PA22/TIOC0A pin for

channel 0 in the MTU2 in high-impedance state when

either POE8F or MTU2CH0HIZ bit is set to 1.

0: Does not place the pin in high-impedance state

1: Places the pin in high-impedance state

12.3.8

Port Output Enable Control Register 2 (POECR2)

POECR2 is a 16-bit readable/writable register that controls high-impedance state of the pins.

01110

00000000

R/W* R/W* R/W*

111

R/W* R/W* R/W*

RRR

Note:

Can be modified only once after a power-on reset.

Bit:

Initial value:

R/W:

MTU2

P1CZE

MTU2

P2CZE

MTU2

P3CZE

MTU2S

P1CZE

MTU2S

P2CZE

MTU2S

P3CZE

---

Bit

Bit Name

Initial

Value

R/W

Description

—

Reserved

This bit is always read as 0. The write value should

always be 0.

MTU2P1CZE

R/W*

MTU2 Port 1 Output Comparison/High-Impedance

Enable

Specifies whether to compare output levels for the

MTU2 high-current PB18/TIOC3B and PB19/TIOC3D

pins and to place them in high-impedance state when

the OSF1 bit is set to 1 while the OCE1 bit is 1 or

when any one of the POE0F, POE1F, POE3F, and

MTU2CH34HIZ bits is set to 1.

0: Does not compare output levels or place the pins in

high-impedance state

1: Compares output levels and places the pins in

high-impedance state

R5F72115D160FPV Datasheet(PDF) 651 Page - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 651 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL