R5F72115D160FPV datasheet(648/1228 Pages) RENESAS

648 / 1228 page

Section 12 Port Output Enable 2 (POE2)

Rev. 2.00 May. 08, 2008 Page 624 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

1, 0

POE8M[1:0] 00

R/W*

POE8 Mode

These bits select the input mode of the

POE8 pin.

00: Accept request on falling edge of

POE8 input

01: Accept request when

POE8 input has been sampled

for 16 P

φ/8 clock pulses and all are low level.

10: Accept request when

POE8 input has been sampled

for 16 P

φ/16 clock pulses and all are low level.

11: Accept request when

POE8 input has been sampled

for 16 P

φ/128 clock pulses and all are low level.

Notes: 1. Only 0 can be written to clear the flag after 1 is read.

2. Can be modified only once after a power-on reset.

12.3.6

Software Port Output Enable Register (SPOER)

SPOER is an 8-bit readable/writable register that controls high-impedance state of the pins.

7654321

00000000

RRRRR

R/W

Bit:

Initial value:

R/W:

-----

MTU2S

HIZ

MTU2

CH0HIZ

MTU2

CH34HIZ

Bit

Bit Name

Initial

Value

R/W

Description

7 to 3 —

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

R5F72115D160FPV Datasheet(PDF) 648 Page - Renesas Technology Corp

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