R5F72115D160FPV datasheet(730/1228 Pages) RENESAS

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Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 May. 08, 2008 Page 706 of 1200

REJ09B0344-0200

In serial transmission, the SCIF operates as described below.

1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the

data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that

the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to

SCFTDR. The number of data bytes that can be written is (16 – transmit trigger setting).

2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive

transmit operations are performed until there is no transmit data left in SCFTDR. When the

number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the

FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register

(SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is

generated.

The serial transmit data is sent from the TXD pin in the following order.

A. Start bit: One-bit 0 is output.

B. Transmit data: 8-bit or 7-bit data is output in LSB-first order.

C. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is

not output can also be selected.)

D. Stop bit(s): One or two 1 bits (stop bits) are output.

E. Mark state: 1 is output continuously until the start bit that starts the next transmission is

sent.

3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is

present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial

transmission of the next frame is started.

R5F72115D160FPV Datasheet(PDF) 730 Page - Renesas Technology Corp