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R5F72115D160FPV Datasheet(PDF) 727 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 727 Page - Renesas Technology Corp |
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727 / 1228 page  Section 15 Serial Communication Interface with FIFO (SCIF) Rev. 2.00 May. 08, 2008 Page 703 of 1200 REJ09B0344-0200 (3) Transmitting and Receiving Data • SCIF Initialization (Asynchronous Mode) Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF as follows. When changing the operating mode or the communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing TE and RE to 0, however, does not initialize the serial status register (SCFSR), transmit FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which retain their previous contents. Clear TE to 0 after all transmit data has been transmitted and the TEND flag in the SCFSR is set. The TE bit can be cleared to 0 during transmission, but the transmit data goes to the Mark state after the bit is cleared to 0. Set the TFRST bit in SCFCR to 1 and reset SCFTDR before TE is set again to start transmission. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCIF operation becomes unreliable if the clock is stopped. |
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