R5F72115D160FPV datasheet(728/1228 Pages) RENESAS

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Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 May. 08, 2008 Page 704 of 1200

REJ09B0344-0200

Figure 15.3 shows a sample flowchart for initializing the SCIF.

Start of initialization

Clear TE and RE bits in SCSCR to 0

Set TFRST and RFRST bits in SCFCR to 1

Set CKE1 and CKE0 in SCSCR

(leaving TIE, RIE, TE, and RE bits cleared to 0)

Set data transfer format in SCSMR

Set value in SCBRR

Set ABCS in SCSEMR

Set RTRG[1:0] and TTRG[1:0] in SCFCR,

and clear TFRST and RFRST

Set TE and RE bits in SCSCR to 1,

and set TIE, RIE, and REIE bits

End of initialization

Set the clock selection in SCSCR.

Be sure to clear bits TIE, RIE, TE,

and RE to 0.

Set the data transfer format in

SCSMR.

Write a value corresponding to the

bit rate into SCBRR. (Not

necessary if an external clock is

used.)

Set the TE bit or RE bit in SCSCR

to 1. Also set the RIE, REIE, and

TIE bits. Setting the TE and RE bits

enables the TxD and RxD pins to be

used.

When transmitting, the SCIF will go

to the mark state; when receiving,

it will go to the idle state, waiting for

a start bit.

[1]

[2]

[3]

[4]

[2]

[3]

[4]

After reading ER, DR, and BRK flags in SCFSR,

and each flag in SCLSR, write 0 to clear them

Figure 15.3 Sample Flowchart for SCIF Initialization

R5F72115D160FPV Datasheet(PDF) 728 Page - Renesas Technology Corp

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