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R5F72115D160FPV Datasheet(PDF) 724 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 724 Page - Renesas Technology Corp |
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724 / 1228 page ![]() Section 15 Serial Communication Interface with FIFO (SCIF) Rev. 2.00 May. 08, 2008 Page 700 of 1200 REJ09B0344-0200 Table 15.9 SCSMR Settings and SCIF Communication Formats SCSMR Settings SCIF Communication Format Bit 7 C/ A Bit 6 CHR Bit 5 PE Bit 3 STOP Mode Data Length Parity Bit Stop Bit Length 0 0 0 0 8 bits Not set 1 bit 1 2 bits 1 0 Set 1 bit 1 2 bits 1 0 0 7 bits Not set 1 bit 1 2 bits 1 0 Set 1 bit 1 Asynchronous 2 bits 1 x x x Clocked synchronous 8 bits Not set None [Legend] x: Don't care Table 15.10 SCSMR and SCSCR Settings and SCIF Clock Source Selection SCSMR SCSCR SCSCR SCIF Transmit/Receive Clock Bit 7 Bit 1 Bit 0 C/ A CKE1 CKE0 Mode Clock Source SCK Pin Function 0 0 SCIF does not use the SCK pin 1 Internal Outputs a clock with a frequency 16 times the bit rate 1 0 External Inputs a clock with frequency 16 times the bit rate 0 1 Asynchronous Setting prohibited 0 x Internal Outputs the serial clock 1 1 0 Clocked synchronous External Inputs the serial clock 1 Setting prohibited [Legend] x: Don't care |
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