R5F72115D160FPV datasheet(805/1228 Pages) RENESAS

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Section 17 A/D Converter (ADC)

Rev. 2.00 May. 08, 2008 Page 781 of 1200

REJ09B0344-0200

17.4

Operation

The A/D converter has two operating modes: single-cycle scan mode and continuous scan mode.

In single-cycle scan mode, A/D conversion is performed once on one or more specified channels

and then it ends. In continuous scan mode, the A/D conversion is performed sequentially on one or

more specified channels until the ADST bit is cleared to 0.

The ADCS bit in the A/D control register (ADCR) is used to select the operating mode. Setting

the ADCS bit to 0 selects single-cycle scan mode and setting the ADCS bit to 1 selects continuous

scan mode. In both modes, A/D conversion starts on the channel with the lowest number in the

analog input channels selected by the A/D analog input channel select register (ADANSR) from

AN0 to AN7.

In single-cycle scan mode, when one cycle of A/D conversion on all specified channels is

completed, the ADF bit in ADSR is set to 1 and the ADST bit is automatically cleared to 0. In

continuous scan mode, when conversion on all specified channels is completed, the ADF bit in

ADSR is set to 1. To stop A/D conversion, write 0 to the ADST bit. When the ADF bit is set to 1,

if the ADIE bit in ADCR is set to 1, an A/D conversion end interrupt (ADI) is generated. When

clearing the ADF bit to 0, read the ADF bit while set to 1 and then write 0. However, when the

DMAC is activated by an ADI interrupt, the ADF bit is automatically cleared to 0.

17.4.1

Single-Cycle Scan Mode

The following example shows the operation when analog input channels 0 to 3 (AN0 to AN3) are

selected and the A/D conversion is performed in single-cycle scan mode using four channels.

1. Set the ADCS bit in the A/D control register (ADCR) to 0.

2. Set all bits ANS0 to ANS3 in the A/D analog input channel select register (ADANSR) to 1.

3. Set the ADST bit in the A/D control register (ADCR) to 1 to start A/D conversion.

4. After channels 0 to 2 (GrA) are sampled simultaneously, offset canceling processing (OFC) is

performed. Then, A/D conversion is performed on channel 0. Upon completion of the A/D

conversion, the A/D conversion result is transferred to ADDR0. Following this, channel 1 is

converted. Upon completion of the conversion, the A/D conversion result is transferred to

ADDR1. In the same way, channel 2 is converted and the A/D conversion result is transferred

to ADDR2.

A/D conversion of channel 3 is then started. Upon completion of the A/D conversion, the A/D

conversion result is transferred to ADDR3.

R5F72115D160FPV Datasheet(PDF) 805 Page - Renesas Technology Corp