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R5F72115D160FPV Datasheet(PDF) 806 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 806 Page - Renesas Technology Corp |
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806 / 1228 page ![]() Section 17 A/D Converter (ADC) Rev. 2.00 May. 08, 2008 Page 782 of 1200 REJ09B0344-0200 5. When A/D conversion ends on all specified channels (AN0 to AN3), the ADF bit is set to 1, the ADST bit is automatically cleared to 0, and the A/D conversion ends. At this time, if the ADIE bit is set to 1, an ADI interrupt is generated after the A/D conversion. ADST ADF S AN0 AN1 AN2 AN3 ADDR0 ADDR1 ADDR2 ADDR3 S H S H OFC H OFC H OFC H OFC Waiting for conversion Waiting for conversion A/D conversion A/D conversion result (AN0) A/D conversion result (AN1) A/D conversion result (AN2) [Legend] ADST set ADST automatically cleared ADF cleared Waiting for conversion A/D conversion Waiting for conversion A/D conversion Waiting for conversion Waiting for conversion Waiting for conversion A/D conversion A/D conversion result (AN3) Waiting for conversion Waiting for conversion A/D conversion execution Simultaneous sampling Simultaneous sampling Simultaneous sampling OFC: S: H: Offset canceling processing Sampling Holding Figure 17.2 Example of A/D_0 Converter Operation (Single-Cycle Scan Mode) |
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