R5F72115D160FPV datasheet(810/1228 Pages) RENESAS

810 / 1228 page

Section 17 A/D Converter (ADC)

Rev. 2.00 May. 08, 2008 Page 786 of 1200

REJ09B0344-0200

Table 17.6

A/D Conversion Time

Number of Required States

Item

Symbol

Min.

Typ.

Max.

A/D conversion start delay time

11*

⎯

15*

Analog input sampling time of dedicated

sample-and-hold circuit for GrA and GrB

SPLSH

⎯

Offset canceling processing time

OFC

⎯

Analog input sampling time of sample-

and-hold circuit common to all channels

SPL

⎯

A/D conversion complete processing

end

⎯

A/D conversion time

CONV

50n + 95*

⎯

50n + 99*

Notes: 1. A/D converter activation by the MTU2 or MTU2S trigger signal.

2. A/D converter activation by an external trigger signal.

3. n: number of A/D conversion channels (n = 1 to 8)

tOFC

OFC

ADDR

Conversion time

per channel

50 states

φ = 40 MHz: 1.25 μs

ADF

ADST

TRGAN

(MTU2, MTU2S trigger signal)

A/D conversion time (tCONV)

Sampling and

hold time (tSPLSH)

Sampling and

hold time (tSPL)

Conversion complete

processing (tend)

A/D

converter

Waiting

Sample-

and-hold

A/D conversion

End of A/D

conversion

Sample-

and-hold

Figure 17.4 A/D Conversion Timing (Single-Cycle Scan Mode)

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