HD64F3664FP datasheet(19/444 Pages) RENESAS

19 / 444 page

Rev. 6.00 Mar. 24, 2006 Page xix of xxviii

Figures

Section 1 Overview

Figure 1.1 Internal Block Diagram of H8/3664 of F-ZTATTM and Mask-ROM Versions ............. 3

Figure 1.2 Internal Block Diagram of H8/3664N of F-ZTATTM Version with EEPROM ............. 4

Figure 1.3 Pin Arrangement of H8/3664 of F-ZTATTM and Mask-ROM Versions

(FP-64E, FP-64A)......................................................................................................... 5

Figure 1.4 Pin Arrangement of H8/3664 of F-ZTATTM and Mask-ROM Versions

(FP-48F, FP-48B) ......................................................................................................... 6

Figure 1.5 Pin Arrangement of H8/3664 of F-ZTATTM and Mask-ROM Versions

(DS-42S)....................................................................................................................... 7

Figure 1.6 Pin Arrangement of H8/3664N of F-ZTATTM Version with EEPROM

(FP-64E) ....................................................................................................................... 8

Section 2 CPU

Figure 2.1 Memory Map (1) ......................................................................................................... 14

Figure 2.1 Memory Map (2) ......................................................................................................... 15

Figure 2.1 Memory Map (3) ......................................................................................................... 16

Figure 2.2 CPU Registers ............................................................................................................. 17

Figure 2.3 Usage of General Registers .........................................................................................18

Figure 2.4 Relationship between Stack Pointer and Stack Area................................................... 19

Figure 2.5 General Register Data Formats (1).............................................................................. 21

Figure 2.5 General Register Data Formats (2).............................................................................. 22

Figure 2.6 Memory Data Formats................................................................................................. 23

Figure 2.7 Instruction Formats...................................................................................................... 34

Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 38

Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 41

Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 42

Figure 2.11 CPU Operation States................................................................................................ 43

Figure 2.12 State Transitions ........................................................................................................ 44

Figure 2.13 Example of Timer Configuration with Two Registers Allocated to

Same Address ........................................................................................................... 45

Section 3 Exception Handling

Figure 3.1 Reset Sequence............................................................................................................ 60

Figure 3.2 Stack Status after Exception Handling ........................................................................ 62

Figure 3.3 Interrupt Sequence....................................................................................................... 63

Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 65

Section 4 Address Break

Figure 4.1 Block Diagram of Address Break................................................................................ 67

HD64F3664FP Datasheet(PDF) 19 Page - Renesas Technology Corp