HD64F3664FP datasheet(20/444 Pages) RENESAS

20 / 444 page

Rev. 6.00 Mar. 24, 2006 Page xx of xxviii

Figure 4.2 Address Break Interrupt Operation Example (1)......................................................... 71

Figure 4.2 Address Break Interrupt Operation Example (2)......................................................... 72

Figure 4.3 Operation when Condition is not Satisfied in Branch Instruction ............................... 73

Figure 4.4 Operation when Another Interrupt is Accepted at

Address Break Setting Instruction ............................................................................... 74

Figure 4.5 Operation when the Instruction Set is not Executed

and does not Branch due to Conditions not Being Satisfied ........................................ 75

Section 5 Clock Pulse Generators

Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 77

Figure 5.2 Block Diagram of System Clock Generator ................................................................ 78

Figure 5.3 Typical Connection to Crystal Resonator.................................................................... 78

Figure 5.4 Equivalent Circuit of Crystal Resonator...................................................................... 78

Figure 5.5 Typical Connection to Ceramic Resonator.................................................................. 79

Figure 5.6 Example of External Clock Input ................................................................................ 79

Figure 5.7 Block Diagram of Subclock Generator ....................................................................... 80

Figure 5.8 Typical Connection to 32.768-kHz Crystal Resonator................................................ 80

Figure 5.9 Equivalent Circuit of 32.768-kHz Crystal Resonator.................................................. 80

Figure 5.10 Pin Connection when not Using Subclock ................................................................ 81

Figure 5.11 Example of Incorrect Board Design .......................................................................... 82

Section 6 Power-Down Modes

Figure 6.1 Mode Transition Diagram ........................................................................................... 88

Section 7 ROM

Figure 7.1 Flash Memory Block Configuration............................................................................ 96

Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode.......................... 103

Figure 7.3 Program/Program-Verify Flowchart ......................................................................... 105

Figure 7.4 Erase/Erase-Verify Flowchart ................................................................................... 108

Section 9 I/O Ports

Figure 9.1 Port 1 Pin Configuration............................................................................................ 115

Figure 9.2 Port 2 Pin Configuration............................................................................................ 121

Figure 9.3 Port 5 Pin Configuration............................................................................................ 124

Figure 9.4 Port 7 Pin Configuration............................................................................................ 130

Figure 9.5 Port 8 Pin Configuration............................................................................................ 133

Figure 9.6 Port B Pin Configuration...........................................................................................138

Section 10 Timer A

Figure 10.1 Block Diagram of Timer A ..................................................................................... 140

Section 11 Timer V

Figure 11.1 Block Diagram of Timer V ..................................................................................... 146

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