H8SLASH3021 datasheet(415/712 Pages) RENESAS

415 / 712 page

11. Serial Communication Interface

Rev.2.00 Mar. 22, 2007 Page 391 of 684

REJ09B0352-0200

TDRE flag in SSR and the start (falling edge) of the first transmit clock pulse corresponding to

each frame (figure 11.22). This interval is also necessary when performing continuous

transmission. If this condition is not satisfied, an operation error may occur.

TDRE

TXD

SCK

Note: Make sure that t is at least 5 states.

Continuous transmission

Figure 11.22 Transmission in Synchronous Mode (Example)

Restrictions when Switching from SCK Pin to Port Function in Synchronous SCI:

1. Problem in Operation

After setting DDR and DR to 1 and using synchronous SCI clock output, when the SCK pin is

switched to the port function at the end of transmission, a low-level signal is output for one half-

cycle before the port output state is established.

When switching to the port function by making the following settings while DDR = 1, DR = 1,

A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, low-level output occurs for one half-cycle.

(1) End of serial data transmission

(2) TE bit = 0

(3) C/

A bit = 0 ... switchover to port output

(4) Occurrence of low-level output (see figure 11.23)

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