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H8/3021 Datasheet(PDF) 414 Page - Renesas Technology Corp

Part # H8/3021
Description  16-Bit Single-Chip Microcomputer
PDF  712 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8/3021 Datasheet(HTML) 414 Page - Renesas Technology Corp

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11. Serial Communication Interface
Rev.2.00 Mar. 22, 2007 Page 390 of 684
REJ09B0352-0200
Internal
base clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
0
7
15 0
7
15 0
D0
D1
8 clocks
16 clocks
Start bit
Figure 11.21 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
1
| D – 0.5 |
M = | ( 0.5 –
2N
) – (L – 0.5) F –
N
(1 + F) |
× 100% ...............(1)
M:
Receive margin (
%)
N:
Ratio of clock frequency to bit rate (N = 16)
D:
Clock duty cycle (D = 0 to 1.0)
L:
Frame length (L = 9 to 12)
F:
Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875
%, as given by equation (2).
When
D = 0.5, F = 0:
M = [0.5 – 1/(2
× 16)] × 100%
= 46.875
%
(2)
This is a theoretical value. A reasonable margin to allow in system design is 20
% to 30%.
Restrictions in Synchronous Mode: When data transmission is performed using an external
clock source as the serial clock, an interval of at least 5 states is necessary between clearing the



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