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H8/3021 Datasheet(PDF) 451 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 451 Page - Renesas Technology Corp |
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451 / 712 page  13. A/D Converter Rev.2.00 Mar. 22, 2007 Page 427 of 684 REJ09B0352-0200 13.2.3 A/D Control Register (ADCR) Bit Initial value Read/Write 7 TRGE 0 R/W 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 0 — 1 — 2 — 1 — 1 — 1 — Trigger enable Enables or disables external triggering of A/D conversion Reserved bits ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion. ADCR is initialized to H'7F by a reset and in standby mode. Bit 7—Trigger Enable (TRGE): Enables or disables external triggering of A/D conversion. Bit 7 TRGE Description 0 A/D conversion cannot be externally triggered (Initial value) 1 A/D conversion starts at the falling edge of the external trigger signal ( ADTRG) Bits 6 to 0—Reserved: These bits cannot be modified and are always read as 1. |
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