H8SLASH3021 datasheet(525/712 Pages) RENESAS

525 / 712 page

16. Clock Pulse Generator

Rev.2.00 Mar. 22, 2007 Page 501 of 684

REJ09B0352-0200

Section 16 Clock Pulse Generator

16.1

Overview

This LSI has a built-in clock pulse generator (CPG) that generates the system clock (

φ) and other

internal clock signals (

φ/2 to φ/4096). After duty adjustment, a frequency divider divides the clock

frequency to generate the system clock (

φ). The system clock is output at the φ pin*1 and furnished

as a master clock to prescalers that supply clock signals to the on-chip supporting modules.

Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the frequency divider by

settings in a division control register (DIVCR).*

2 Power consumption in the chip is reduced in

almost direct proportion to the frequency division ratio.

Notes: 1. Usage of the

φ pin differs depending on the chip operating mode and the PSTOP bit

setting in the module standby control register (MSTCR). For details, see section 17.7,

System Clock Output Disabling Function.

2. The division ratio of the frequency divider can be changed dynamically during

operation. The clock output at the

φ pin also changes when the division ratio is

changed. The frequency output at the

φ pin is shown below.

φ = EXTAL × n

EXTAL:

Frequency of crystal resonator or external clock signal

Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8)

H8/3021 Datasheet(PDF) 525 Page - Renesas Technology Corp