H8SLASH3021 datasheet(521/712 Pages) RENESAS

521 / 712 page

15. ROM

Rev.2.00 Mar. 22, 2007 Page 497 of 684

REJ09B0352-0200

Flash memory access disabled time

(x: Wait time after SWE setting, y: Wait time after SWE clearing)*3

Flash memory reprogammable period

(Flash memory program execution and data read, other than verify, are disabled.)

VCC

FWE

tOSC1

Min 0

μs

tMDS

tRESW

MD2 to MD0

RES

SWE bit

Mode switching*1

Mode

switching*1

Boot mode

User

mode

User

mode

User program mode

User

program

mode

SWE set

SWE clear

Notes: 1. In transition to the boot mode and transition from the boot mode to another mode, mode switching via

RES

input is necessary.

During this switching period (period during which a low level is input to the

RES pin), the state of the address

dual port and bus control output signals (

AS, RD, WR) changes.

Therefore, do not use these pins as output signals during this switching period.

2. When making a transition from the boot mode to another mode, the mode programming setup time tMDS

relative to the

RES clear timing is necessary.

3. See section 18.2.5 Flash Memory Characteristics.

Figure 15.19 Mode Transition Timing

(Example: Boot mode

→ User mode ↔ User program mode)

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