H8SLASH3021 datasheet(557/712 Pages) RENESAS

557 / 712 page

18. Electrical Characteristics

Rev.2.00 Mar. 22, 2007 Page 533 of 684

REJ09B0352-0200

Table 18.6

Timing of On-Chip Supporting Modules

Conditions: V

CC = 3.0 V to 3.6 V, AVCC = 3.6 V to 5.5 V, VSS = AVSS = 0 V,

φ = 2 MHz to 18 MHz, T

a = –20°C to +75°C

Module

Item

Symbol

Min

Max

Unit

Test

Conditions

ITU

Timer output delay time

TOCD

—

100

Figure 18.15

Timer input setup time

TICS

—

Timer clock input setup time

TCKS

—

Figure 18.16

Single edge

TCKWH

1.5

—

cyc

Timer clock

pulse width

Both edges

TCKWL

2.5

—

SCI

Asynchronous

Scyc

—

Figure 18.17

Input clock

cycle

Synchronous

—

Input clock rise time

SCKr

—

1.5

Input clock fall time

SCKf

—

1.5

Input clock pulse width

SCKW

0.4

0.6

Scyc

Transmit data delay time

TXD

—

100

Figure 18.18

Receive data setup time

(synchronous)

RXS

100

—

Receive data hold time

(synchronous clock input)

RXH

100

—

Receive data hold time

(synchronous clock output)

—

Ports and

Output data delay time

PWD

—

100

Figure 18.14

TPC

Input data setup time

PRS

—

Input data hold time

PRH

—

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