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H8/3021 Datasheet(PDF) 628 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 628 Page - Renesas Technology Corp |
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628 / 712 page  Appendix B. Internal I/O Register Field Rev.2.00 Mar. 22, 2007 Page 604 of 684 REJ09B0352-0200 TMDR—Timer Mode Register H'62 ITU (all channels) Bit Initial value Read/Write 7 — 1 — 6 MDF 0 R/W 5 FDIR 0 R/W 4 PWM4 0 R/W 3 PWM3 0 R/W 0 PWM0 0 R/W 2 PWM2 0 R/W 1 PWM1 0 R/W PWM mode 0 0 Channel 0 operates normally 1 Channel 0 operates in PWM mode PWM mode 3 0 Channel 3 operates normally 1 Channel 3 operates in PWM mode PWM mode 1 0 Channel 1 operates normally 1 Channel 1 operates in PWM mode PWM mode 2 0 Channel 2 operates normally 1 Channel 2 operates in PWM mode PWM mode 4 0 Channel 4 operates normally 1 Channel 4 operates in PWM mode Flag direction 0 OVF is set to 1 in TSR2 when TCNT2 overflows or underflows 1 OVF is set to 1 in TSR2 when TCNT2 overflows Phase counting mode flag 0 Channel 2 operates normally 1 Channel 2 operates in phase counting mode |
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