 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
H8/3021 Datasheet(PDF) 104 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
H8/3021 Datasheet(HTML) 104 Page - Renesas Technology Corp |
|
|
104 / 712 page  5. Interrupt Controller Rev.2.00 Mar. 22, 2007 Page 80 of 684 REJ09B0352-0200 5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. ISCR IER IPRA, IPRB . . . OVF TME ADI ADIE . . . . . . . CPU CCR I UI UE SYSCR I: IER: IPRA: IPRB: ISCR: ISR: SYSCR: UE: UI: NMI input IRQ input IRQ input section ISR Interrupt controller Priority decision logic Interrupt request Vector number Interrupt mask bit IRQ enable register Interrupt priority register A Interrupt priority register B IRQ sense control register IRQ status register System control register User bit enable User bit/interrupt mask bit Legend Figure 5.1 Interrupt Controller Block Diagram |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
