H8SLASH3021 datasheet(105/712 Pages) RENESAS

105 / 712 page

5. Interrupt Controller

Rev.2.00 Mar. 22, 2007 Page 81 of 684

REJ09B0352-0200

5.1.3

Pin Configuration

Table 5.1 lists the interrupt pins.

Table 5.1

Interrupt Pins

Name

Abbreviation

I/O

Function

Nonmaskable interrupt

NMI

Input

Nonmaskable interrupt, rising edge or

falling edge selectable

External interrupt

request 5, 4, 1, and 0

IRQ

4 , and

IRQ

1 , IRQ0

Input

Maskable interrupts, falling edge or level

sensing selectable

5.1.4

Table 5.2 lists the registers of the interrupt controller.

Table 5.2

Interrupt Controller Registers

Address*

Name

Abbreviation

R/W

Initial Value

H'FFF2

System control register

SYSCR

R/W

H'0B

H'FFF4

IRQ sense control register

ISCR

R/W

H'00

H'FFF5

IRQ enable register

IER

R/W

H'00

H'FFF6

IRQ status register

ISR

R/(W)*

H'00

H'FFF8

Interrupt priority register A

IPRA

R/W

H'00

H'FFF9

Interrupt priority register B

IPRB

R/W

H'00

Notes: 1. Lower 16 bits of the address.

2. Only 0 can be written, to clear flags.

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