H8SLASH3021 datasheet(312/712 Pages) RENESAS

312 / 712 page

9. Programmable Timing Pattern Controller

Rev.2.00 Mar. 22, 2007 Page 288 of 684

REJ09B0352-0200

9.1.2

Block Diagram

Figure 9.1 shows a block diagram of the TPC.

PADDR

NDERA

TPMR

PBDDR

NDERB

TPCR

Internal

data bus

Control logic

ITU compare match signals

Pulse output

pins, group 3

PBDR

PADR

Legend

TPMR:

TPCR:

NDERB:

NDERA:

PBDDR:

PADDR:

NDRB:

NDRA:

PBDR:

PADR:

Pulse output

pins, group 2

Pulse output

pins, group 1

Pulse output

pins, group 0

TPC output mode register

TPC output control register

Next data enable register B

Next data enable register A

Port B data direction register

Port A data direction register

Next data register B

Next data register A

Port B data register

Port A data register

NDRB

NDRA

(

Since this LSI does not have this pin, this signal cannot be output to the outside.

Note: *

Figure 9.1 TPC Block Diagram

H8/3021 Datasheet(PDF) 312 Page - Renesas Technology Corp

H8/3021 Datasheet(HTML) 312 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL