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H8/3028F Datasheet(PDF) 342 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 342 Page - Renesas Technology Corp |
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342 / 923 page ![]() Rev. 2.00, 09/03, page 312 of 890 Block Diagram of Channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical. Both have the structure shown in figure 9.2. Clock selector Comparator Control logic TCLKA to TCLKD φ, φ/2, φ/4, φ/8 TIOCA0 TIOCB0 IMIA0 IMIB0 OVI0 Module data bus Legend: 16TCNT: GRA, GRB: TCR: TIOR: Timer counter (16 bits) General registers A and B (input capture/output compare registers) (16 bits 2) Timer control register (8 bits) Timer I/O control register (8 bits) × Figure 9.2 Block Diagram of Channels 0 and 1 |
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