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H8/3028F Datasheet(PDF) 343 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 343 Page - Renesas Technology Corp |
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343 / 923 page ![]() Rev. 2.00, 09/03, page 313 of 890 Block Diagram of Channel 2: Figure 9.3 is a block diagram of channel 2 Clock selector Comparator Control logic TCLKA to TCLKD φ, φ/2, φ/4, φ/8 TIOCA2 TIOCB2 IMIA2 IMIB2 OVI2 Module data bus Legend: 16TCNT2: GRA2, GRB2: TCR2: TIOR2: Timer counter 2 (16 bits) General registers A2 and B2 (input capture/output compare registers) (16 bits × 2) Timer control register 2 (8 bits) Timer I/O control register 2 (8 bits) Figure 9.3 Block Diagram of Channel 2 |
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