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H8/3028F Datasheet(PDF) 398 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 398 Page - Renesas Technology Corp |
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398 / 923 page ![]() Rev. 2.00, 09/03, page 368 of 890 Contention between General Register Write and Input Capture: If an input capture signal occurs in the T3 state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 9.44. φ Address bus Internal write signal Input capture signal 16TCNT GR M GR address General register write cycle T1 T2 T3 M Figure 9.44 Contention between General Register Write and Input Capture |
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