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H8/3028F Datasheet(PDF) 402 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 402 Page - Renesas Technology Corp |
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402 / 923 page ![]() Rev. 2.00, 09/03, page 372 of 890 Table 9.7 (c) 16-bit timer Operating Modes (Channel 2) Register Settings TSNC TMDR TIOR2 16TCR2 Synchro- Clear Clock Operating Mode nization MDF FDIR PWM IOA IOB Select Select Synchronous preset SYNC2 = 1 — PWM mode — PWM2 = 1 — * Output compare A — PWM2 = 0 IOA2 = 0 Other bits unrestricted Output compare B — IOB2 = 0 Other bits unrestricted Input capture A — PWM2 = 0 IOA2 = 1 Other bits unrestricted Input capture B — PWM2 = 0 IOB2 = 1 Other bits unrestricted Counter By compare — CCLR1 = 0 clearing match/input CCLR0 = 1 capture A By compare — CCLR1 = 1 match/input CCLR0 = 0 capture B Syn- SYNC2 = 1 — CCLR1 = 1 chronous CCLR0 = 1 clear Phase counting MDF = 1 — mode Legend: Setting available (valid). — Setting does not affect this mode. Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited. |
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