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H8/3028F Datasheet(PDF) 425 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 425 Page - Renesas Technology Corp |
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425 / 923 page  Rev. 2.00, 09/03, page 395 of 890 φ CMFB Input capture signal 8TCNT N N TCORB Figure 10.15 CMFB Flag Setting Timing when Input Capture Occurs Timing of Overflow Flag (OVF) Setting: The OVF flag in 8TCSR is set to 1 by the overflow signal generated when 8TCNT overflows (from H'FF to H'00). Figure 10.16 shows the timing in this case. φ OVF Overflow signal 8TCNT H'FF H'00 Figure 10.16 Timing of OVF Setting 10.4.5 Operation with Cascaded Connection If bits CKS2 to CKS0 are set to (100) in either 8TCR0 or 8TCR1, the 8-bit timers of channels 0 and 1 are cascaded. With this configuration, the two timers can be used as a single 16-bit timer (16-bit timer mode), or channel 0 8-bit timer compare matches can be counted in channel 1 (compare match count mode). Similarly, if bits CKS2 to CKS0 are set to (100) in either 8TCR2 or 8TCR3, the 8-bit timers of channels 2 and 3 are cascaded. With this configuration, the two timers can be used as a single 16-bit timer (16-bit timer mode),or channel 2 8-bit timer compare matches can be counted in channel 3 (compare match count mode). In this case, the timer operates as below. |
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