H8SLASH3028F datasheet(444/923 Pages) RENESAS

444 / 923 page

Rev. 2.00, 09/03, page 414 of 890

11.1.4

Registers

Table 11.2 summarizes the TPC registers.

Table 11.2 TPC Registers

Address*

Name

Abbreviation

R/W

Function

H'EE009

Port A data direction register

PADDR

H'00

H'FFFD9

Port A data register

PADR

R/(W)*

H'00

H'EE00A

Port B data direction register

PBDDR

H'00

H'FFFDA

Port B data register

PBDR

R/(W)*

H'00

H'FFFA0

TPC output mode register

TPMR

R/W

H'F0

H'FFFA1

TPC output control register

TPCR

R/W

H'FF

H'FFFA2

Next data enable register B

NDERB

R/W

H'00

H'FFFA3

Next data enable register A

NDERA

R/W

H'00

H'FFFA5/

H'FFFA7*

Next data register A

NDRA

R/W

H'00

H'FFFA4/

H'FFFA6*

Next data register B

NDRB

R/W

H'00

Notes: 1. Lower 20 bits of the address in advanced mode.

2. Bits used for TPC output cannot be written.

3. The NDRA address is H'FFFA5 when the same output trigger is selected for TPC

output groups 0 and 1 by settings in TPCR. When the output triggers are different, the

NDRA address is H'FFFA7 for group 0 and H'FFFA5 for group 1. Similarly, the address

of NDRB is H'FFFA4 when the same output trigger is selected for TPC output groups 2

and 3 by settings in TPCR. When the output triggers are different, the NDRB address is

H'FFFA6 for group 2 and H'FFFA4 for group 3.

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