H8SLASH3028F datasheet(447/923 Pages) RENESAS

447 / 923 page

Rev. 2.00, 09/03, page 417 of 890

11.2.5

Next Data Register A (NDRA)

NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups

1 and 0 (pins TP7 to TP0). During TPC output, when an 16-bit timer compare match event

specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The

address of NDRA differs depending on whether TPC output groups 0 and 1 have the same output

trigger or different output triggers.

NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by

the same compare match event, the NDRA address is H'FFFA5. The upper 4 bits belong to group

1 and the lower 4 bits to group 0. Address H'FFFA7 consists entirely of reserved bits that cannot

be modified and always read 1.

Address H'FFFA5

Bit

Initial value

Read/Write

NDR0

R/W

NDR1

R/W

NDR2

R/W

NDR3

R/W

NDR4

R/W

NDR5

R/W

NDR6

R/W

NDR7

R/W

Next data 7 to 4

These bits store the next output

data for TPC output group 1

Next data 3 to 0

These bits store the next output

data for TPC output group 0

Address H'FFFA7

Bit

Initial value

Read/Write

—

Reserved bits

H8/3028F Datasheet(PDF) 447 Page - Renesas Technology Corp

H8/3028F Datasheet(HTML) 447 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL