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H8/3028F Datasheet(PDF) 450 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 450 Page - Renesas Technology Corp |
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450 / 923 page  Rev. 2.00, 09/03, page 420 of 890 Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFFA4 and the address of the lower 4 bits (group 2) is H'FFFA6. Bits 3 to 0 of address H'FFFA4 and bits 7 to 4 of address H'FFFA6 are reserved bits that cannot be modified and always read 1. Address H'FFFA4 Bit Initial value Read/Write 0 — 1 — 1 — 1 — 2 — 1 — 3 — 1 — 4 NDR12 0 R/W 5 NDR13 0 R/W 6 NDR14 0 R/W 7 NDR15 0 R/W Next data 15 to 12 These bits store the next output data for TPC output group 3 Reserved bits Address H'FFFA6 Bit Initial value Read/Write 0 NDR8 0 R/W 1 NDR9 0 R/W 2 NDR10 0 R/W 3 NDR11 0 R/W 4 — 1 — 5 — 1 — 6 — 1 — 7 — 1 — Next data 11 to 8 These bits store the next output data for TPC output group 2 Reserved bits |
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