H8SLASH3028F datasheet(452/923 Pages) RENESAS

452 / 923 page

Rev. 2.00, 09/03, page 422 of 890

11.2.8

Next Data Enable Register B (NDERB)

NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2

(TP15 to TP8) on a bit-by-bit basis.

Bit

Initial value

Read/Write

NDER8

R/W

NDER9

R/W

NDER10

R/W

NDER11

R/W

NDER12

R/W

NDER13

R/W

NDER14

R/W

NDER15

R/W

Next data enable 15 to 8

These bits enable or disable

TPC output groups 3 and 2

If a bit is enabled for TPC output by NDERB, then when the 16-bit timer compare match event

selected in the TPC output control register (TPCR) occurs, the NDRB value is automatically

transferred to the corresponding PBDR bit, updating the output value. If TPC output is disabled,

the bit value is not transferred from NDRB to PBDR and the output value does not change.

NDERB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC

output groups 3 and 2 (TP15 to TP8) on a bit-by-bit basis.

Bits 7 to 0

NDER15 to NDER8

Description

TPC outputs TP15 to TP8 are disabled

(NDR15 to NDR8 are not transferred to PB7 to PB0)

(Initial value)

TPC outputs TP15 to TP8 are enabled

(NDR15 to NDR8 are transferred to PB7 to PB0)

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