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H8/3028F Datasheet(PDF) 448 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 448 Page - Renesas Technology Corp |
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448 / 923 page  Rev. 2.00, 09/03, page 418 of 890 Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFFA5 and the address of the lower 4 bits (group 0) is H'FFFA7. Bits 3 to 0 of address H'FFFA5 and bits 7 to 4 of address H'FFFA7 are reserved bits that cannot be modified and always read 1. Address H'FFFA5 Bit Initial value Read/Write 0 — 1 — 1 — 1 — 2 — 1 — 3 — 1 — 4 NDR4 0 R/W 5 NDR5 0 R/W 6 NDR6 0 R/W 7 NDR7 0 R/W Next data 7 to 4 These bits store the next output data for TPC output group 1 Reserved bits Address H'FFFA7 Bit Initial value Read/Write 0 NDR0 0 R/W 1 NDR1 0 R/W 2 NDR2 0 R/W 3 NDR3 0 R/W 4 — 1 — 5 — 1 — 6 — 1 — 7 — 1 — Next data 3 to 0 These bits store the next output data for TPC output group 0 Reserved bits |
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